An active-matrix type display device displays an image by selecting pixel circuits arranged two-dimensionally in unit of row and writing voltages in accordance with image data to the selected pixel circuits. In order to select the pixel circuits in unit of row, a shift register for sequentially shifting an output signal based on a clock signal is used as a scanning line drive circuit. Furthermore, in a display device for performing a dot sequential drive, a similar shift register is provided inside a data line drive circuit.
In a liquid crystal display device or the like, a drive circuit of the pixel circuits may be formed integrally with the pixel circuits using a manufacturing process for forming a TFT (Thin Film Transistor) in the pixel circuit. In this case, in order to reduce a manufacturing cost, it is preferable to form the drive circuit including the shift register with transistors having a same conductive type as the TFT.
Regarding the shift register, various circuits are conventionally known. For example, Patent Document 1 describes a shift register 900 shown in FIG. 27. The shift register 900 has a configuration in which unit circuits 901 shown in FIG. 28 are connected in multi-stage. The shift register 900 performs a normal operation, when an initialization signal INIT and an all-on control signal AON are at a low level and a negative signal AONB of the all-on control signal is at a high level. At this time, transistors Q7, Q9, Q11 turn off and transistors Q8, Q10 turn on.
The normal operation of the unit circuit 901 will be described below. At first, when an input signal IN changes to the high level, a transistor Q3 turns on, a potential of a node N1 becomes the high level, the node N1 becomes a floating state, and a transistor Q1 turns on. Since a clock signal CKA is at the low level at this time, an output signal OUT is at the low level. Furthermore, when the input signal IN changes to the high level, a transistor Q5 turns on, and potentials of nodes N2, N3 become the low level. Next, when the input signal IN becomes the low level, the transistors Q3, Q5 turn off.
Next, when, the clock signal CKA changes to the high level, the output signal OUT becomes the high level. At this time, the potential of the node N1 is pushed up via a capacitor Cv and parasitic capacitance of the transistor Q1, and the potential of the node N1 becomes higher than (VDD+Vth) (Vth is a threshold voltage of the TFT). Thus, a potential of the output signal OUT becomes VDD. Next, when the clock signal CKA changes to the low level, the potential of the node N1 returns to an original high level and the output signal OUT becomes the low level.
Next, when a clock signal CKB changes to the high level, a transistor Q6 turns on, the potentials of the nodes N2, N3 become the high level, and the nodes N2, N3 become the floating state. Thus, transistors Q2, Q4 turn on and the potential of the node N1 becomes the low level. Next, when the clock signal CKB changes to the low level, the transistor Q6 turns off.
After that, the clock signal CKB becomes the high level and the low level in a predetermined cycle. In a high level period of the clock signal CKB, the transistor Q6 turns on and a high level potential is applied to the nodes N2, N3. In a low level period of the clock signal CKB, the transistor Q6 turns off and the nodes N2, N3 keep the high level potential in the floating state.
If the node N2 is in the floating state when the output signal OUT is at the high level, the potential of the node N2 fluctuates due to noise imposed on the output signal OUT, the transistor Q2 may turn on, and the shift register 900 may malfunction. A transistor Q12 has a function of fixing the potential of the node N2 to the low level when the output signal OUT is at the high level. Transistors Q14, Q15 have a function of setting the potential of the node N2 to the high level when both of input signals IN, BIN are at the high level. It is possible to make the shift register 900 more reliable by providing the transistors Q12, Q14, Q15.
The shift register 900 operates in accordance with a timing chart shown in FIG. 29, when a power is turned on. When the initialization signal INIT and the all-on control signal AON change to the high level and the negative signal AONB of the all-on control signal changes to the low level, the transistors Q7, Q9, Q11 turn on and the transistors Q8, Q10 turn off. Thus, the potential of the node N2 becomes the low level and the potential of the node N3 becomes the high level. Accordingly, the transistor Q2 turns off, the transistor Q4 turns on, the potential of the node N1 becomes the low level, and the transistor Q1 turns off. In this manner, since the transistors Q1, Q2 turn off and the transistor Q7 turns on, the output signal OUT becomes the high level and the transistor Q12 turns on. Hereinafter, an operation for setting the output signals of all of the unit circuits to the on level (here, high level) is referred to as all-on output.
Next, when the all-on control signal AON changes to the low level and the negative signal AONB of the all-on control signal changes to the high level, the transistors Q7, Q11 turn off and the transistors Q8, Q10 turn on. At this time, the potential of the node N2 becomes the high level, the transistor Q2 turns on, the output signal OUT becomes the low level, and the transistor Q12 turns off. Hereinafter, an operation for setting the output signals of all of the unit circuits to the off level (here, low level) is referred to as initialization.
The shift register 900 performs the all-on output and the initialization when the power is turned on. Therefore, it is possible to set the potential of the node N1 and the output signal OUT to the low level and set the potentials of the nodes N2, N3 to the nigh level in all of the unit circuits 901, before a start signal ST supplied to the input terminal IN of the unit circuit 901 in a first stage changes to the high level.